december 2003 p2040c rev 1.0 alliance semiconductor 2575, augustine drive ? santa clara, ca ? tel: 408.855.4900 ? fax: 408.855.4999 ? www.alsc.com notice: the information in this document is subject to change without notice. lcd panel emi reduction ic features ? fcc approved method of emi attenuation. ? provides up to 15 db of emi suppression ? generates a low emi spread spectrum clock of the input frequency ? 50 mhz to 170 mhz input frequency range ? optimized for 54mhz, 65mhz, 81mhz, 140mhz, and 162mhz pixel clock frequencies ? internal loop filter minimizes external components and board space ? 8 selectable spread ranges, up to +/- 2.2% ? sson# control pin for spread spectrum enable and disable options ? 2 selectable m odulation rates ? low cycle-to-cycle jitter ? 3.3v operating voltage ? 16 ma output drives ? ttl or cmos compatible outputs ? ultra low power cmos design ? supports most mobile graphic accelerator and lcd timing controller specifications ? available in 8 pin soic and tssop product description the p2040c is a selectable spread spectrum frequency modulator designed specifically for digital flat panel applications. the p2040c r educes electromagnetic interference (emi) at the clock source which provides system wide reduction of emi of all clock dependent signals. the p2040c allows significant system cost savings by reducing the number of circuit board layers and shielding that are traditionally required to pass emi regulations. the p2040c uses the most efficient and optimized modulation profile approved by the fcc and is implemented in a proprietary all-digital method. the p2040c modulates the output of a single pll in order to ?spread? the bandwidth of a synthesized clock and, more importantly, decreas es the peak amplitudes of its harmonics. this results in significantly lower system emi compared to the typical narrow band signal produced by oscillators and most frequency generators. lowering emi by increasing a signal?s bandwidth is called ?spread spectrum clock generation?. applications the p2040c is targeted towards digital flat panel applications for notebook pcs, palm-size pcs, office automation equipments, and lcd monitors.
december 2003 p2040c rev 1.0 lcd panel emi reduction ic 2 of 9 notice: the information in this document is subject to change without notice. mra 1 2 3 4 5 6 7 8 p2040c clkin s r1 vss sson# modout sr0 v dd block diagram pin configuration pin description pin# pin name type description 1 clkin i external reference frequency input. co nnect to externally generated reference signal. 2 mra i digital logic input used to select modulation rate. this pin has an internal pull-up resistor. 3 sr1 i digital logic input used to select spreading range. this pin has an internal pull-up resistor. 4 vss p ground to entire chip. connect to system ground. 5 sson# i digital logic input used to enable spread spectrum function (active low). spread spectrum function enabled when low, disabled when high. this pin has an internal pull-low resistor. 6 modout o spread spectrum clock output. 7 sr0 i digital logic input used to select spreading range. this pin has an internal pull-up resistor. 8 vdd p power supply for the entire chip (3.3v) clkin modout vss frequency divider feedback divider modulation phase detector loop filter vco output divider pll vdd sson# sr0 sr1 mra
december 2003 p2040c rev 1.0 lcd panel emi reduction ic 3 of 9 notice: the information in this document is subject to change without notice. 1 2 3 4 clkin mra sr1 vss sr0 5 6 7 8 sson# modout vdd p2040c modulation selection (commercial) ? table 1 spreading range mra sr1 sr0 54 mhz 65 mhz 81 mhz 108 mhz 162 mhz modulation rate 0 0 0 +/-1.4% +/-1.2% +/-1.0% +/-0.8% +/-0.4% (fin/80) * 62.49 khz 0 0 1 +/-2.0% +/-1.9% +/-1.6% +/-1.2% +/-0.8% (fin/80) * 62.49 khz 0 1 0 +/-1.1% +/-0.9% +/-0.5% +/-0.4% +/-0.3% (fin/80) * 62.49 khz 0 1 1 +/-1.8% +/-1.5% +/-1.0% +/-0.6% +/-0.4% (fin/80) * 62.49 khz 1 0 0 +/-1.3% +/-1.3% +/-1.3% +/-1.2% +/-1.1% (fin/80) * 20.83 khz 1 0 1 +/-2.2% +/-2.1% +/-2.1% +/-1.9% +/-1.8% (fin/80) * 20.83 khz 1 1 0 +/-1.4% +/-1.3% +/-1.4% +/-1.2% +/-0.9% (fin/80) * 20.83 khz 1 1 1 +/-2.1% +/-2.1% +/-2.1% +/-2.0% +/-1.4% (fin/80) * 20.83 khz spread spectrum selection table 1 illustrates the possible spread spectrum options. the optimal setting should minimize system emi to the fullest without affecting system performance. the spreading is described as a percentage deviation of the center frequency (note: the center frequency is the frequency of the external reference input on clkin, pin 1). example : p2040c is designed for high resolution flat panel applications and is able to support panel frequencies from 54mhz to 170mhz. for a 65mhz pixel clock frequen cy, a spreading selection of mra=0, sr1=1 and sr0=1 provides a percentage deviation of +/ -1.50% (see table 1). this results in frequency on modout being swept from 64.03mhz to 65.98mhz at a modul ation rate of 50.77khz (see table 1). this particular example (see figure below) given here is a common emi reduction method for notebook lcd panel and has already been implemented by most of the leading oem and mobile graphic accelerator manufacturers. p2040c application schematic for mobile lcd graphics 65mhz from g raphics accelerator modulated 65mhz signal with 0.75 deviation and modulation rate of 56.24khz. this signal is connected back to the spread spectrum input pin (ssin) of the graphics accelerator. + 3.3v 0.1f digital control for the ss enable or disable
december 2003 p2040c rev 1.0 lcd panel emi reduction ic 4 of 9 notice: the information in this document is subject to change without notice. emc software simulation by using alliance emi-lator? 1 electromagnetic interference simulation software, radiated system level emi analysis can be made easier to allow a quantitative assess ment of emi reduction products. the simulation engine of this emc software has already been characterized to corr elate to the electrical char acteristics of the alliance emi reduction ics. the following illust ration is an example of the simulation result. please visit our website at www.alsc.com for information on how to obtain a free copy and a demonstration of the emi-lator simulation software. simulation results from emi-lator?
december 2003 p2040c rev 1.0 lcd panel emi reduction ic 5 of 9 notice: the information in this document is subject to change without notice. absolute maximum ratings symbol parameter rating unit v dd , v in voltage on any pin with respect to gnd -0.5 to +7.0 v t stg storage temperature -65 to +125 oc t a operating temperature 0 to +70 oc note: these are stress ratings only and are not implied for functional use. exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. dc electrical characteristics symbol parameter min typ max unit v il input low voltage gnd ? 0.3 - 0.8 v v ih input high voltage 2.0 - v dd + 0.3 v i il input low current (pull-up resistor on inputs sr0, 1 and mra) - - -35 a i ih input high current (pull-down resistor on input sson#) - - 35 a v ol output low voltage (vdd=3.3v, iol = 20 ma) - - 0.4 v v oh output high voltage (vdd=3.3v, ioh = 20 ma) 2.5 - - v i dd static supply current - 0.6 - ma i cc dynamic supply current (3.3v and 15 pf loading) 9 16 22 ma v dd operating voltage 2.7 3.3 3.7 v t on power up time (first locked clock cycle after power up) 0.18 ms z out clock output impedance 50 ? ac electrical characteristics symbol parameter min typ max unit f in input frequency, p2040c 50 120 175 mhz t lh * output rise time (0.8v to 2.0v) 0.7 0.9 1.1 ns t hl * output fall time (2.0v to 0.8v) 0.6 0.8 1.0 ns t jc jitter (cycle to cycle) - - 360 ps t d output duty cycle 45 50 55 % *t lh and t hl are measured into a capacitive load of 15pf package information
december 2003 p2040c rev 1.0 lcd panel emi reduction ic 6 of 9 notice: the information in this document is subject to change without notice. d e h d a1 a2 a l c b e 8-pin soic dimensions in inches dimensions in millimeters symbol min max min max a 0.057 0.071 1.45 1.80 a1 0.004 0.010 0.10 0.25 a2 0.053 0.069 1.35 1.75 b 0.012 0.020 0.31 0.51 c 0.004 0.01 0.10 0.25 d 0.186 0.202 4.72 5.12 e 0.148 0.164 3.75 4.15 e 0.050 bsc 1.27 bsc h 0.224 0.248 5.70 6.30 l 0.012 0.028 0.30 0.70 0 8 0 8 8-pin tssop
december 2003 p2040c rev 1.0 lcd panel emi reduction ic 7 of 9 notice: the information in this document is subject to change without notice. e h a a1 a2 d b c l e dimensions in inches dimensions in millimeters symbol min max min max a 0.047 1.10 a1 0.002 0.006 0.05 0.15 a2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.114 0.122 2.90 3.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.244 0.260 6.20 6.60 l 0.018 0.030 0.45 0.75 0 8 0 8
december 2003 p2040c rev 1.0 lcd panel emi reduction ic 8 of 9 notice: the information in this document is subject to change without notice. ordering information part number marking package type qty/reel temperature a2040c-08st a2040c 8-pin soic, tube -40c to 125c A2040C-08SR a2040c 8-pin soic, t ape & reel 2500 -40c to 125c a2040c-08tt a2040c 8-pin tssop, tube -40c to 125c a2040c-08tr a2040c 8-pin tssop, tape & reel 2500 -40c to 125c i2040c-08st i2040c 8-pin soic, tube -40c to 125c i2040c-08sr i2040c 8-pin soic, tape & reel 2500 -40c to 125c i2040c-08tt i2040c 8-pin tssop, tube -40c to 125c i2040c-08tr i2040c 8-pin tssop, tape & reel 2500 -40c to 125c p2040c-08st p2040c 8-pin soic, tube 0c to 70c p2040c-08sr p2040c 8-pin soic, tape & reel 2500 0c to 70c p2040c-08tt p2040c 8-pin tssop, tube 0c to 70c p2040c-08tr p2040c 8-pin tssop, tape & reel 2500 0c to 70c part numbering guide x 2040 c 08 xx 1 2 3 4 5 1. flow prefix: a. a = automotive temperature range (-40c to 125c) b. i = industrial temperature range (-40c to 85c) c. c = commercial temperature range (0c to 70) 2. device number 3. deviation (%) and spread option identifier 4. device pin count 5. package identifier a. st ? soic in tube b. sr ? soic in tape & reel c. tt ? tssop in tube d. tr ? tssop in tape & reel licensed under us patent #5,488,627, #6,646,463 and #5,631,920.
december 2003 p2040c rev 1.0 lcd panel emi reduction ic 9 of 9 notice: the information in this document is subject to change without notice. ? copyright 2003 alliance semiconductor corporation. all right s reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alli ance. all other brand and product names ma y be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at an y time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data containe d herein represents alliance's best data and/or estimates at the time of issuance. alliance re serves the right to change or correct this data at any time, without notice. if the product described herein is under developm ent, significant changes to thes e specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provid e, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any expres s or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellec tual property rights, except as express agreed to in allian ce's terms and conditions of sale (which are available from a lliance). all sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as cr itical components in life-suppor ting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the incl usion of alliance products in su ch life-supporting systems implies that the manufacturer assumes all risk of such us e and agrees to indemnify alliance against all claims arising from such use. alliance semiconductor corporation 2595, augustine drive, santa clara, ca 95054 tel# 408-855-4900 fax: 408-855-4999 www.alsc.com copyright ? alliance semiconductor all rights reserved preliminary information part number: p2040c document version: v1.0 note: this product utilizes us patent # 6,646,463 impedance emulator patent issued to alliance semiconductor, dated 11-11-2003
|
